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1/20 xc6118 series voltage detector with separated sense pin & delay capacitor pin general description the xc6118 series is a low power consumption voltage detect or with high accuracy detection, manufactured using cmos process and laser trimming technologies. since the sense pin is separated from the power supply pin, it allows the ic to monitor the other power supply. the xc6118 can maintain the state of detection even when voltage of the monitored power supply drops to 0v. moreover, a release delay time can be adjusted by t he external capacitor connected to the cd pin. the v out pin is available in both cmos and n-ch annel open drain output configurations. a pplications microprocessor reset circuitry charge voltage monitors memory battery back-up switch circuits power failure detection circuits features high accuracy : 2 (detect voltage R 1.5v) : 30mv(detect voltage 1.5v) low power consumption : 0.4 a(detect, v in =1.0v) (typ.) : 0.8 a(release, v in =1.0v)(typ.) detect voltage range : 0.8v 5.0v (0.1v increments) operating voltage range : 1.0v 6.0v temperature characteristics : 100ppm/ (typ.) output configuration : cmos, n-channel open drain operating temperature range : -40 +85 separated sense pin : power supply separation built-in delay time : release delay time adjustable packages : usp-4, sot-25 environmentall y friendl y : eu rohs com p liant , pb free typical application circuit typical performance characteristics output voltage vs. sense voltage etr0213-004 e? xc6118c25agr -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0123456 sense voltage: vsen (v) output voltage: vout (v) ta=25 4.0v 1.0v vin=6.0v monitering power supply (no pull-up resistor needed for cmos output product)
2/20 xc6118 series pin number usp-4 sot-25 pin name function 1 1 v out output (detect ?l?) 2 5 cd delay capacitance (*1) 2 - nc no connection 3 4 v sen sense 4 3 v in input 5 2 v ss ground (*2) designator description symbol description c cmos output output configuration n n-ch open drain output ? detect voltage 08~50 e.g. 18 1.8v a built-in delay capacitance pin, hysteresis 5% (typ.)(standard*) b built-in delay capacitance pin, hy steresis less than 1%(standard*) c no built-in delay capacitance pin, hysteresis 5% (typ.) (semi-custom) options d no built-in delay capacitance pin, hysteresis less than 1% (semi-custom) gr-g usp-4 (halogen & antimony free) ? - packages taping type (*2) mr-g sot-25 (halogen & antimony free) pin configuration pin assignment product classification ordering information xc6118 ?????- (*1) 3 vsen 4 vin cd/nc 2 vout 1 usp-4 bottom view sot-25 top view note: *1: with the v ss pin of the usp-4 package, a tab on the backside is used as the pin no.5. *2: in the case of selecting no built-in delay capaci tance pin type, the delay capacitance (cd) pin will be used as the nc. * in the xc6118xxxa/b series, the dissipation pad should not be short-circui ted with other pins. * in the xc6118xxxc/d series, when the dissipation pad is short-circuited with other pins, connect it to the nc pin (no.2) pin before use. 5 vss *when delay function isn?t used, open the delay capacitance pin before use. (*1) the ?-g? suffix indicates that the products are halo gen and antimony free as well as being fully rohs compliant. (*2) the device orientation is fixed in its embossed tape pocket. for reverse orientation, please contact your local torex sales office or representative. (standard orientation: r- , reverse orientation: l- )
3/20 xc6118 series block diagrams (1) xc6118cxxa *the delay capacitance pin (cd) is not connected to the circuit in the block diagram of xc6118cxxc (semi-custom). *the delay capacitance pin (cd) is not connected to the circuit in the block diagram of xc6118cxxd (semi-custom). *the delay capacitance pin (cd) is not connected to the circuit in the block diagram of xc6118nxxc (semi-custom). *the delay capacitance pin (cd) is not connected to the circuit in the block diagram of xc6118nxxd (semi-custom). (2) xc6118cxxb (3) xc6118nxxa (4) xc6118nxxb
4/20 xc6118 series xc6118xxxa/b xc6118xxxc/d parameter symbol ratings units input voltage v in v ss -0.3 7.0 v output current i out 10 ma xc6118c (*1) v ss -0.3 v in +0.3 output voltage xc6118n (*2) v out v ss -0.3 7.0 v sense pin voltage v sen v ss -0.3 7.0 v delay capacitance pin voltage v cd v ss -0.3 v in +0.3 v delay capacitance pin current i cd 5.0 ma usp-4 120 power dissipation sot-25 pd 250 mw operating temperature range ta -40 +85 o c storage temperature range tstg -55 +125 o c parameter symbol ratings units input voltage v in v ss -0.3 7.0 v output current i out 10 ma xc6118c (*1) v ss -0.3 v in +0.3 output voltage xc6118n (*2) v out v ss -0.3 7.0 v sense pin voltage v sen v ss -0.3 7.0 v usp-4 120 power dissipation sot-25 pd 250 mw operating temperature range ta -40 +85 o c storage temperature range tstg -55 +125 o c a bsolute maximum ratings note: *1: cmos output *2: n-ch open drain output ta = 2 5 ta = 2 5
5/20 xc6118 series parameter symbol conditions min. typ. max. units circuits operating voltage v in v df(t) =0.8 5.0v (*1) 1.0 6.0 v - detect voltage v df v in =1.0 6.0v e-1 v hysteresis width v hys v in =1.0 6.0v e-2 v detect voltage line regulation v df / ( v in ? v df ) v in =1.0 6.0v 0.1 %/v supply current 1 (*2) i ss1 v sen =v df 0.9 v in =1.0v v in =6.0v 0.4 0.4 1.0 1.0 a supply current 2 (*2) i ss2 v sen =v df 1.1 v in =1.0v v in =6.0v 0.8 0.9 1.6 1.8 a i out1 v sen =0v, v ds =0.5v(nch) v in =1.0v v in =2.0v v in =3.0v v in =4.0v v in =5.0v v in =6.0v 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 ma output current (*3) i out2 v sen =6.0v, v ds =0.5v(pch) v in =1.0v v in =6.0v -0.30 -1.00 -0.08 -0.70 ma cmos output 0.20 leakage current n-ch open drain output i leak v in =6.0v, v sen =6.0v, v out =6.0v, cd: open 0.20 0.40 a temperature characteristics v df / ( t opr ? v df ) -40 o c Q t a Q 85 o c 100 ppm/ o c sense resistance (*4) r sen v sen =5.0v v in =0v e-4 m delay resistance (*5) r delay v sen =6.0v v in =5.0v cd=0v 1.6 2.0 2.4 m delay capacitance pin sink current i cd cd=0.5v, v in =1.0v 200 a delay capacitance pin threshold voltage v tcd v sen =6.0v v in =1.0v v sen =6.0v v in =6.0v 0.4 2.9 0.5 3.0 0.6 3.1 v undefined operation (*6) v uns v in =v sen =0 1.0v 0.3 0.4 v detect delay time (*7) t df0 v in =6.0v, v sen =6.0 0v cd: open 30 230 s release delay time (*8) t dr0 v in =6.0v, v sen =0 6.0v cd: open 30 200 s electrical characteristics xc6118xxxa ta = 2 5 note: *1: v df (t) : nominal detect voltage *2: current to the sense resistor is not included. *3: i out2 is applied only to the xc6118c series (cmos output). *4: it is calculated from the voltage value and the current value of the v sen . *5: it is calculated from the voltage value of the v in and the current value of the cd. *6: maximum v out voltage when v in is changed from 0v to 1.0v under connecting the v in pin to the v sen pin. this value is effective only to the xc6118c series (cmos output). *7: delay time from the time of v sen =v df to the time of v out = 0.6v when the v sen falls. *8: delay time from the time of v in = v df +v hys to the time of v out = 5.4v when the v sen rises.
6/20 xc6118 series parameter symbol conditions min. typ. max. units circuits operating voltage v in v df(t) =0.8 5.0v (*1) 1.0 6.0 v - detect voltage v df v in =1.0 6.0v e-1 v hysteresis width v hys v in =1.0 6.0v e-3 v detect voltage line regulation v df / ( v in ? v df ) v in =1.0 6.0v 0.1 %/v supply current 1 (*2) i ss1 v sen =v df 0.9 v in =1.0v v in =6.0v 0.4 0.4 1.0 1.0 a supply current 2 (*2) i ss2 v sen =v df 1.1 v in =1.0v v in =6.0v 0.8 0.9 1.6 1.8 a i out1 v sen =0v v ds =0.5v(nch) v in =1.0v v in =2.0v v in =3.0v v in =4.0v v in =5.0v v in =6.0v 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 ma output current (*3) i out2 v sen =6.0v v ds =0.5v(pch) v in =1.0v v in =6.0v -0.30 -1.00 -0.08 -0.70 ma cmos output 0.20 leakage current n-ch open drain output i leak v in =6.0v, v sen =6.0v, v out =6.0v, cd: open 0.20 0.40 a temperature characteristics v df / ( t opr ? v df ) -40 o c Q t a Q 85 o c 100 ppm/ o c sense resistance (*4) r sen v sen =5.0v v in =0v e-4 m delay resistance (*5) r delay v sen =6.0v v in =5.0v cd=0v 1.6 2.0 2.4 m delay capacitance pin sink current i cd cd=0.5v, v in =1.0v 200 a delay capacitance pin threshold voltage v tcd v sen =6.0v v in =1.0v v sen =6.0v v in =6.0v 0.4 2.9 0.5 3.0 0.6 3.1 v undefined operation (*6) v uns v in =v sen =0 1.0v 0.3 0.4 v detect delay time (*7) t df0 v in =6.0v, v sen =6.0 0v cd: open 30 230 s release delay time (*8) t dr0 v in =6.0v, v sen =0 6.0v cd: open 30 200 s electrical characteristics (continued) xc6118xxxb ta = 2 5 note: *1: v df (t) : nominal detect voltage *2: current to the sense resistor is not included. *3: i out2 is applied only to the xc6118c series (cmos output). *4: it is calculated from the voltage value and the current value of the v sen . *5: it is calculated from the voltage value of the v in and the current value of the cd. *6: maximum v out voltage when v in is changed from 0v to 1.0v under connecting the v in pin to the v sen pin. this value is effective only to the xc6118c series (cmos output). *7: delay time from the time of v sen =v df to the time of v out = 0.6v when the v sen falls. *8: delay time from the time of v in = v df +v hys to the time of v out = 5.4v when the v sen rises.
7/20 xc6118 series parameter symbol conditions min. typ. max. units circuits operating voltage v in v df(t) =0.8 5.0v (*1) 1.0 6.0 v - detect voltage v df v in =1.0 6.0v e-1 v hysteresis width v hys v in =1.0 6.0v e-2 v detect voltage line regulation v df / ( v in ? v df ) v in =1.0 6.0v 0.1 %/v supply current 1 (*2) i ss1 v sen =v df 0.9 v in =1.0v v in =6.0v 0.4 0.4 1.0 1.0 a supply current 2 (*2) i ss2 v sen =v df 1.1 v in =1.0v v in =6.0v 0.8 0.9 1.6 1.8 a i out1 v sen =0v v ds =0.5v(nch) v in =1.0v v in =2.0v v in =3.0v v in =4.0v v in =5.0v v in =6.0v 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 ma output current (*3) i out2 v sen =6.0v v ds =0.5v(pch) v in =1.0v v in =6.0v -0.30 -1.00 -0.08 -0.70 ma cmos output 0.20 leakage current nch open drain output i leak v in =6.0v, v sen =6.0v, v out =6.0v, cd: open 0.20 0.40 a temperature characteristics v df / ( t opr ? v df ) -40 o c Q t a Q 85 o c 100 ppm/ o c sense resistance (*4) r sen v sen =5.0v v in =0v e-4 m undefined operation (*5) v uns v in =v sen =0 1.0v 0.3 0.4 v detect delay time (*6) t df0 v in =6.0v, v sen =6.0 0v 30 230 s release delay time (*7) t dr0 v in =6.0v, v sen =0 6.0v 30 200 s electrical characteristics ( continued ) xc6118xxxc ta = 2 5 note: *1: v df (t) : nominal detect voltage *2: current to the sense resistor is not included. *3: i out2 is applied only to the xc6118c series (cmos output). *4: it is calculated from the voltage value and the current value of the v sen . *5: maximum v out voltage when v in is changed from 0v to 1.0v under connecting the v in pin to the v sen pin. this value is effective only to the xc6118c series (cmos output). *6: delay time from the time of v sen =v df to the time of v out = 0.6v when the v sen falls. *7: delay time from the time of v in = v df +v hys to the time of v out = 5.4v when the v sen rises.
8/20 xc6118 series parameter symbol conditions min. typ. max. units circuits operating voltage v in v df(t) =0.8 5.0v (*1) 1.0 6.0 v - detect voltage v df v in =1.0 6.0v e-1 v hysteresis width v hys v in =1.0 6.0v e-3 v detect voltage line regulation v df / ( v in ? v df ) v in =1.0 6.0v 0.1 %/v supply current 1 (*2) i ss1 v sen =v df 0.9 v in =1.0v v in =6.0v 0.4 0.4 1.0 1.0 a supply current 2 (*2) i ss2 v sen =v df 1.1 v in =1.0v v in =6.0v 0.8 0.9 1.6 1.8 a i out1 v sen =0v v ds =0.5v(nch) v in =1.0v v in =2.0v v in =3.0v v in =4.0v v in =5.0v v in =6.0v 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 ma output current (*3) i out2 v sen =6.0v v ds =0.5v(pch) v in =1.0v v in =6.0v -0.30 -1.00 -0.08 -0.70 ma cmos output 0.20 leakage current nch open drain output i leak v in =6.0v, v sen =6.0v, v out =6.0v, cd: open 0.20 0.40 a temperature characteristics v df / ( t opr ? v df ) -40 o c Q t a Q 85 o c 100 ppm/ o c sense resistance (*4) r sen v sen =5.0v v in =0v e-4 m undefined operation (*5) v uns v in =v sen =0 1.0v 0.3 0.4 v detect delay time (*6) t df0 v in =6.0v v sen =6.0 0v 30 230 s release delay time (*7) t dr0 v in =6.0v v sen =0 6.0v 30 200 s electrical characteristics ( continued ) note: *1: v df (t) : nominal detect voltage *2: current to the sense resistor is not included. *3: i out2 is applied only to the xc6118c series (cmos output). *4: it is calculated from the voltage value and the current value of the v sen . *5: maximum v out voltage when v in is changed from 0v to 1.0v under connecting the v in pin to the v sen pin. this value is effective only to the xc6118c series (cmos output). *6: delay time from the time of v sen =v df to the time of v out = 0.6v when the v sen falls. *7: delay time from the time of v in = v df +v hys to the time of v out = 5.4v when the v sen rises.
9/20 xc6118 series symbol e-1 e-2 e-3 e-4 parameter nominal voltage detect voltage (*1) (v) hysteresis range (v) hysteresis range (v) sense resistance (m ) v df v hys v hys r sen v df(t) (v) min. max. min. max. min. max. min. typ. 0.8 0.770 0.830 0.015 0.066 0.008 0.9 0.870 0.930 0.017 0.074 0.009 1.0 0.970 1.030 0.019 0.082 0.010 1.1 1.070 1.130 0.021 0.090 0.011 1.2 1.170 1.230 0.023 0.098 0.012 1.3 1.270 1.330 0.025 0.106 0.013 1.4 1.370 1.430 0.027 0.114 0.014 1.5 1.470 1.530 0.029 0.122 0.015 1.6 1.568 1.632 0.031 0.131 0.016 1.7 1.666 1.734 0.033 0.085 0.017 1.8 1.764 1.836 0.035 0.147 0.018 1.9 1.862 1.938 0.037 0.155 0.019 10 20 2.0 1.960 2.040 0.039 0.163 0.020 2.1 2.058 2.142 0.041 0.171 0.021 2.2 2.156 2.244 0.043 0.180 0.022 2.3 2.254 2.346 0.045 0.188 0.023 2.4 2.352 2.448 0.047 0.196 0.024 2.5 2.450 2.550 0.049 0.204 0.026 2.6 2.548 2.652 0.051 0.212 0.027 2.7 2.646 2.754 0.053 0.220 0.028 2.8 2.744 2.856 0.055 0.228 0.029 2.9 2.842 2.958 0.057 0.237 0.030 3.0 2.940 3.060 0.059 0.245 0.031 3.1 3.038 3.162 0.061 0.253 0.032 3.2 3.136 3.264 0.063 0.261 0.033 3.3 3.234 3.366 0.065 0.269 0.034 3.4 3.332 3.468 0.067 0.277 0.035 3.5 3.430 3.570 0.069 0.286 0.036 3.6 3.528 3.672 0.071 0.294 0.037 3.7 3.626 3.774 0.073 0.302 0.038 3.8 3.724 3.876 0.074 0.310 0.039 3.9 3.822 3.978 0.076 0.318 0.040 13 24 4.0 3.920 4.080 0.078 0.326 0.041 4.1 4.018 4.182 0.080 0.335 0.042 4.2 4.116 4.284 0.082 0.343 0.043 4.3 4.214 4.386 0.084 0.351 0.044 4.4 4.312 4.488 0.086 0.359 0.045 4.5 4.410 4.590 0.088 0.367 0.046 4.6 4.508 4.692 0.090 0.375 0.047 4.7 4.606 4.794 0.092 0.384 0.048 4.8 4.704 4.896 0.094 0.392 0.049 4.9 4.802 4.998 0.096 0.400 0.050 5.0 4.900 5.100 0.098 0.408 0 0.051 15 28 voltage chart note: *1: when v df(t) Q 1.4v, the detection accuracy is 30mv. when v df(t) R 1.5v, the detection accuracy is 2%.
10/20 xc6118 series circuit 1 circuit 2 circuit 3 circuit 4 circuit 5 circuit 6 circuit 7 circuit 8 circuit 9 *no delay capacitance pin availabl e in the xc6118xxxc/d series. r=100k (no resistor needed for cmos output products) r=100k (no resistor needed for cmos output products) r=100k (no resistor needed for cmos output products) waveform measurement point vin vsen cd vss vout a xc6118 series vin vsen cd vss vout a xc6118 series vin vsen cd vss vout a xc6118 series vin vsen cd vss vout v v xc6118 series vin vsen cd vss vout v xc6118 series test circuits
11/20 xc6118 series a typical circuit example is shown in figure 1, and the timing chart of figure 1 is shown in figure 2. as an early state, the sense pin is applie d sufficiently high voltage (6.0v max.) an d the delay capacitance (cd) is charged to the power supply input voltage, (v in : 1.0v min., 6.0v max.). while the sense pin voltage (v se n ) starts dropping to reach the detect voltage (v df ) (v sen >v df ), the output voltage (v out ) keeps the ?high? level (=v in ). * if a pull-up resistor of the xc6118n series (n-ch open drai n) is connected to added power supply different from the input voltage pin, the ?high? level will be a voltage value where the pull-up resistor is connected. when the sense pin voltage keeps dropping and becomes equal to the detect voltage (v sen =v df ), an n-ch transistor (m1) for the delay capacitance (cd) discharge is turned on, and starts to discharge the delay capacitance (cd). an inverter (inv . 1) operates as a comparator of the reference voltage v in , and the output voltage changes into the ?low? level (=v ss ). the detect delay time [t df ] is defined as time which ranges from v sen =v df to the v out of ?low? level (especially, when the cd pin is not connected: t df0 ). while the sense pin voltage keeps below the detect voltage, t he delay capacitance (cd) is discharged to the ground voltage (=v ss ) level. then, the output voltage mainta ins the ?low? level while the sense pin voltage increases again to reach the release voltage (v sen < v df +v hys ). operational explanation figure 1: typical application circuit example figure 2: the timing chart of figure 1 *the xc6118n series (n-ch open drain output) requires a pull-up resistor for pulling up output. sense pin voltage: v sen (min.:0v max.:6.0v) delay capacitance pin threshold voltage: v tcd release voltage: v df +v hys output voltage pin voltage: v out (min.:v ss max:v in ) delay capacitance pin voltage: v cd (min.:v ss, max.:v in ) detect voltage: v df vref comparator inverter r 1 r 2 r 3 m 5 en =r 1 +r 2 +r 3 m 2 m1 m3 v out v ss r delay c d v sen v in v in v sen c d m4
12/20 xc6118 series when the sense pin voltage continues to increase up to the release voltage level (v df +v hys ), the n-ch transistor (m1) for the delay capacitance (cd) discharge will be turned off, and t he delay capacitance (cd) will start discharging via a delay resistor (rdelay). the inverter (inv . 1) will operate as a comparat or (rise logic threshold: v tlh =v tcd , fall logic threshold: v thl =v ss ) while the sense pin voltage keeps higher than the detect voltage (v sen > v df ). while the delay capacitance pin voltage (v cd ) rises to reach the delay capacitance pin threshold voltage (v tcd ) with the sense pin voltage equal to the release voltage or higher, the s ense pin will be charged by the time constant of the rc series circuit. assuming the time to the release delay time (t dr ), it can be given by the formula (1). t dr =-r delay cd ln(1-v tcd /v in ) (1) the release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0m (typ.) and the delay capacitance pin voltage is v in /2 (typ.) t dr =r delay cd 0.69 (2) * r delay is 2.0m ? typ. as an example, presuming that the delay capacitance is 0.68 f, t dr is : 2.0 10 6 0.68 10 -6 0.69=938(ms) * note that the release delay time may remarkably be short when the delay capacitance (cd) is not discharged to the ground (=v ss ) level because time described in is short. when the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (v cd =v tcd ), the inverter (inv.1) will be inverted. as a result, the output voltage changes into the ?high? (=v in ) level. t dr0 is defined as time which ranges from v sen =v df +v hys to the v out of ?high? level without connecting to the cd. while the sense voltage is higher than the detect voltage (v sen > v df ), the delay capacitance pin is charged until the delay capacitance pin voltage becomes the input voltage level. therefore, the output volt age maintains the ?high?(=v in ) level. function chart transition of v out condition *1 v sen cd l h l l l h h ? l l ? l h l ? l h h h ? h release delay time chart delay capacitance [cd] ( f) release delay time [t dr ] (typ.) (ms) release delay time [t dr ] *2 (min. ~ max.) (ms) 0.010 13.8 11.0 ~ 16.6 0.022 30.4 24.3 ~ 36.4 0.047 64.9 51.9 ~ 77.8 0.100 138 110 ~ 166 0.220 304 243 ~ 364 0.470 649 519 ~ 778 1.000 1380 1100 ~ 1660 *1: v out transits from condition to because of the combination of v sen and cd. example ex. 1) v out ranges from ?l? to ?h? in case of v sen = ?h? (v dr R v sen ), cd=?h? (v tcd R cd) while v out is ?l?. ex. 2) v out maintains ?h? when cd ranges from ?h? to ?l?, v sen =?h? and cd=?l? when v out becomes ?h? in ex.1. operational explanation (continued) * the release delay time values above are calculated by using the formula (2). *2: the release delay time (t dr ) is influenced by the delay capacitance cd.
13/20 xc6118 series vsen cd vss vin vout vsen vin cd r=100k vout (no resistor needed fo r cmos output products) notes on use figure 3: circuit example with the delay capacitance pin (cd) connected to a schottky barrier diode note r off =v out /i leak figure 4: circuit example of xc6118n series 1. use this ic within the stated maximum ratings. operat ion beyond these limits may cause degrading or permanent damage to the device. 2. the power supply input pin voltage drops by the resistance between power supply and the v in pin, and by through current at operation of the ic. at this time, the operation may be wrong if the power supply input pin voltage falls below the minimum operating voltage range. in cmos output, fo r output current, drops in the power supply input pin voltage similarly occur. moreover, in cmos output, when the v in pin and the sense pin are short-circuited and used, oscillation of the circuit may occur if the drops in voltage, which caused by through current at operation of the ic, ex ceed the hysteresis voltage. note it especially when you use the ic with the v in pin connected to a resistor. 3. when the setting voltage is less than 1.0v, be sure to separate the v in pin and the sense pin, and to apply the voltage over 1.0v to the v in pin. 4. note that a rapid and high fluct uation of the power supply input pin vo ltage may cause a wrong operation. 5. power supply noise may cause operational function erro rs, care must be taken to put the capacitor between v in -gnd and test on the board carefully. 6. when there is a possibility of which t he power supply input pin voltage falls rapidly (e.g.: 6.0v to 0v) at release operatio n with the delay capacitance pin (cd) connected to a capaci tor, use a schottky barrier diode connected between the v in pin and the cd pin as the figure 3 shown below. 7. in n channel open drain output, v out voltage at detect and release is determi ned by resistance of a pull up resistor connected at the v out pin. please choose proper resistance values with refer to figure 4; during detection: v out = v pull / (1+r pull / r on ) v pull : pull up voltage r on ( 1) on resistance of n channel driver m3 can be calculated as v ds / i out1 from electrical characteristics, for example, when ( 2) r on = 0.5 / 0.8 10 -3 = 625 ? min. at v in =2.0v, v pull = 3.0v and v out Q 0.1v at detect, r pull = (v pull /v out -1) r on = (3 / 0.1-1) 625 P 18 in this case, r pull should be selected higher or equal to 18k in order to keep the output voltage less than 0.1v during detection. ( 1) r on is bigger when v in is smaller, be noted. ( 2) for calculation, minimum v in should be chosen among the input voltage range. during releasing v out = v pull / (1 + r pull / r off ) v pull pull up voltage r off on resistance of n channel driver m3 is 15m ? min. when the driver is off (as to v out / i leak ) for example when v pull = 6.0v and v out R 5.99v, r pull = (v pull / v out -1) r off = (6/5.99-1) 15 10 6 P 25 k in this case, r pull should be selected smaller or equal to 25 k in order to obtain output vo ltage higher than 5.99v during releasing. vref comparator inverter r 1 r 2 r 3 m 5 en =r 1 +r 2 +r 3 m 2 m1 m3 v out v ss r delay c d v sen v in v in v sen c d m4
14/20 xc6118 series typical performance characteristics (1) supply current vs. sense voltage (3) detect voltage vs. ambient temperature (2) supply current vs. input voltage (4) detect voltage vs. input voltage xc6118c25ax 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0123456 input voltage: vin (v) supply current: iss ( a) vsen=2.25v 25 -40 ta=85 xc6118c25ax 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0123456 input voltage: vin (v) supply current: iss ( a) vsen=2.75v 25 -40 ta=85 xc6118c25ax 0.0 0.5 1.0 1.5 2.0 0123456 sense voltage: vsen (v) supply current: iss ( a) vin=3.0v 25 -40 ta=85 xc6118c25ax 2.45 2.50 2.55 -50-25 0 25 50 75100 ambient temperature: ta ( ) detect voltage: vdf (v) vin=4.0v xc6118c25ax 2.45 2.50 2.55 1.0 2.0 3.0 4.0 5.0 6.0 input voltage: vin (v) detect voltage: vdf (v) 85 ta=25 -40
15/20 xc6118 series (5) hysteresis voltage vs. ambient temperature typical performance characteristics (continued) (6) cd pin sink current vs. input voltage (7) output voltage vs. sense voltage (8) output voltage vs. input voltage (9) output current vs. input voltage xc6118c25ax 0.05 0.10 0.15 0.20 -50 -25 0 25 50 75 100 ambient temperature: ta ( ) hysteresis voltage: vhys (v) vin=4.0v xc6118c25ax 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0123456 input voltage : vin (v) cd pin current: icd (ma) vsen=0v vds=0.5v 25 85 ta=-40 xc6118n25ax -1.0 0.0 1.0 2.0 3.0 4.0 0 0.5 1 1.5 2 2.5 3 input voltage : vin (v) output voltage: vout (v) vsen=vin pull-up=vin r=100k 25 -40 ta=85 xc6118c25ax -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0123456 sense voltage: vsen (v) output voltage: vout (v) ta=25 4.0v 1.0v vin=6.0v xc6118c25ax 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0123456 input voltage : vin (v) output current: iout (ma) vds(nch)=0.5v ta=- 40 25 85 xc6118c25ax -2.0 -1.5 -1.0 -0.5 0.0 0123456 input voltage : vin (v) output current: iout (ma) vds(pch)=0.5v -40 25 ta=85
16/20 xc6118 series (10) delay resistance vs. ambient temperature typical performance characteristics (continued) (11) release delay time vs. delay capacitance (12) detect delay time vs. delay capacitance (13) leakage current vs. ambient temperature (14) leakage current vs. supply voltage xc6118c25ax 1 10 100 1000 0.0001 0.001 0.01 0.1 1 delay capacitor: cd ( f) detect delay time: tdf ( s) ta=25 vin=6.0v 4.0v 3.0v 2.0v 1.0v xc6118n25ax 0.10 0.15 0.20 0.25 -50 -25 0 25 50 75 100 ambient temperature: ta ( ) leak current: ileak ( a) vin=vsen=6.0v vout=6.0v xc6118n25ax 0.10 0.15 0.20 0.25 0123456 output voltage: vout (v) leak current: ileak ( a) vin=vsen=6.0v xc6118c25ax 1 1.5 2 2.5 3 3.5 4 -50 -25 0 25 50 75 100 ambient temperature: ta ( ) delay resistance: rdelay (m ) vsen=6.0v vcd=0.0v vin=5.0v xc6118c25ax 0.1 1 10 100 1000 10000 0.0001 0.001 0.01 0.1 1 delay capacitor: cd ( f) release delay time: tdr (ms) ta=25 t dr =cd2.010 6 0.69 vin=1.0v 3.0v 6.0v
17/20 xc6118 series packaging information usp-4 sot-25 usp-4 reference pattern layout usp-4 reference metal mask design 43 12 0.6 0.35 0.35 1.0 0.3 0.5 0.3 1.9 1.6 +0.2 -0.1 2.80.2 1.10.1 1.3max 0.2min
18/20 xc6118 series cmos output (xc6118c series) n-ch open drain output (xc6118n series) mark voltage (v) l 0.x m 1.x n 2.x p 3.x r 4.x s 5.x mark voltage (v) t 0.x u 1.x v 2.x x 3.x y 4.x z 5.x mark voltage (v) product series 3 x.3 xc6118**3*** 0 x.0 xc6118**0*** mark options product series a built-in delay capacitance pin with hysteresis 5% (typ.) (standard) xc6118***a** b built-in delay capacitance pin with hysteresis less than 1% (standard) xc6118***b** c no built-in delay capacitance pin with hysteresis 5% (typ.) (semi-custom) xc6118***c** d no built-in delay capacitance pin with hysteresis less than 1% (semi-custom) xc6118***d** marking rule sot-25 represents output configuration and integer number of detect voltage sot-25 (top view) represents decimal number of detect voltage (ex.) represents options ? represents production lot number 0 to 9 a to z, or inverted charac ters of 0 to 9, a to z repeated. (g, i, j, o, q, and w excluded) *no character inversion used. 123 54
19/20 xc6118 series cmos output (xc6118c series) n-ch open drain output (xc6118n series) mark voltage (v) l 0.x m 1.x n 2.x p 3.x r 4.x s 5.x mark voltage (v) t 0.x u 1.x v 2.x x 3.x y 4.x z 5.x mark voltage (v) product series 3 x.3 xc6118**3*** 0 x.0 xc6118**0*** mark options product series a built-in delay capacitance pin with hysteresis 5% (typ.) (standard) xc6118***a** b built-in delay capacitance pin with hysteresis less than 1% (standard) xc6118***b** c no built-in delay capacitance pin with hysteresis 5% (typ.) (semi-custom) xc6118***c** d no built-in delay capacitance pin with hysteresis less than 1% (semi-custom) xc6118***d** marking rule (continued) usp-4 represents output configuration and integer number of detect voltage represents decimal number of detect voltage (ex.) represents options ? represents production lot number 0 to 9, a to z or inverted charac ters of 0 to 9, a to z repeated. (g, i, j, o, q, and w excluded) *no character inversion used. usp-4 (top view) 1 2 4 3
20/20 xc6118 series 1. the products and product specifications cont ained herein are subject to change without notice to improve performance characteristic s. consult us, or our representatives before use, to confirm that the informat ion in this datasheet is up to date. 2. we assume no responsibility for any infri ngement of patents, pat ent rights, or other rights arising from the use of any information and circuitry in this datasheet. 3. please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. the products in this datasheet are not devel oped, designed, or approved for use with such equipment whose failure of malfuncti on can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. atomic energy; aerospace; transpor t; combustion and associated safety equipment thereof.) 5. please use the products listed in this datasheet within the specified ranges. should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. we assume no responsibility for damage or loss due to abnormal use. 7. all rights reserved. no part of this dat asheet may be copied or reproduced without the prior permission of torex semiconductor ltd.

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